SYNTHINGS is a digital synthesizer development platform that I've been building.


jason | 09 December, 2010 20:16

One of my earlier projects had an SPI slave, but this needed to be an SPI master - so I wrote one that had my requirements:

  • Had a configurable speed
  • Had a configurable mode (although SPI mode 0 was all I needed)
  • Had an interrupt
  • Had the enable pin programmable independantly of TX/RX
  • Was asynchronous to the CPU (so if you were writing, the ACK would be given as soon as the byte was available to write).

What I didn't need was a configurable bit length - it would be a multiple of 8 bytes.

Writing a byte to address 1 will initiate a transfer - and also clear the IRQ (which will be set when the transfer is coplete).

Reception is done during transmission; reading address 1 will read the last byte received - no matter how many reads are performed. If an SPI device does not receive data (or doesn't need data for that phase), then a dummy write needs to be performed.

I was able to successfully get the SPI bus to read the manufacturer and device ID from the Flash memory device - nice. However, the SDRAM stopped working properly - I suspect the movement of the CLBs in the FPGA has caused some timing issues which I'll sort out next.

Powered by LifeType - Design by BalearWeb and Jason Tribbeck
Copyright © 2010 | | Jason Tribbeck
All trademarks are the property of their respective owners