SYNTHINGS is a digital synthesizer development platform that I've been building.

More complete Wishbone implementation

jason | 11 December, 2010 17:32

After writing the previous blog entry, I decided to modify all the modules so they would use the more correct Wishbone CYC_/ACK_ timing model, and also implement the STB_ signals (even though they would be a duplicate of the CYC_ signal).

Due to the simplification of the state machines, the number of used cells became smaller (ISE should've optimised away the duplicate signals).

I also did some experiments with the optimisation levels, and found that the SDRAM still worked if I'd selected optimise for area rather than speed - which fills me with hope that I won't need to debug that again!

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