SYNTHINGS is a digital synthesizer development platform that I've been building.

My Wishbone implementation (Wishbone-ST)

jason | 11 December, 2010 14:22

All of my wishbone modules weren't actually wishbone compatible modules - I'd used some of the basic ideas, and simplified the architecture a bit.

The variations to the wishbone interface are:

  • No STB_ signal
  • No SEL_ signals
  • No pipeline
  • No errors or retries
  • No tags
  • Optional IRQ_ signals
  • Optional CLQ_ signals
  • ACK_O/CYC_I timing

Just because something hasn't been implemented now, it doesn't mean that it won't (or can't) be in the future. To prevent confusion with the normal Wishbone architecture, I've labelled these changes as Wishbone-ST.

No STB_ signals

Since most of the operations I'm performing are monotomic and only fetch one data signal, these were always the same (see the Wishone B4 specification, section 3.1.4, permission 3.40). In order to reduce the possibility of errors (and finger fatigue), I decided early on in my work with wishbone that I didn't need this overhead.

No SEL_ signals

Pretty much all of my operations are on a single byte - the exception is the SDRAM, and I decided that they would always be 16-bit in nature. As a result, the SEL_ signals are not reqiured.

No pipeline

The SDRAM and SRAM interfaces would be the only things to benefit from a pipeline. Since the SRAM interface also implements the video output, the video is effectively pipelined - but this is done without a wishbone interface. The SDRAM would be used for samples - and pipelining that would have a limited benefit: sample playback doesn't tax memory too much - at 48KHz, it would require 96KHz bandwidth; a single SDRAM access takes 90ns, which gives 11MHz total bandwidth. 96KHz would be <1% of the total bandwidth (I can have 115 96KHz audio streams running at the same time - ignoring refresh overheads).

No wishbone optional signals

I'm not worried about these. The only one that might be relevant is the SDRAM initialisation - what will currently happen if a Wishbone master wants to access the SDRAM during initialisation is that it will block until it is ready.

No tags

I've got nothing to tag!

Optional IRQ_ signals

The IRQ_ signals are used for the interrupt generation unit to signal an interrupt for the CPU. Most of the modules I've used for testing implement an IRQ.

Optional CLQ_ signals

The CLQ_ signals are used to indicate that the CPU wants the IRQ to be cleared because it has dealt with it. Normally, interrupts would be cleared by the CPU performing an action on the module, but in some cases (such as the HSYNC/VSYNC video interrupts), there is nothing that the module will do with instructions from the CPU, and the interrupts are just informational.

ACK_O/CYC_I timing

This is perhaps the biggest change - the slave will only deassert ACK_O when CYC_I has been deasserted. This means the slave knows that the master has finished with it, and the master can delay processing the input. It also prevents the slave from processing a bogus request from the master if the master doesn't deassert CYC_I as soon as it knows ACK_O has been asserted.

It does introduce an additional wait state though, so I may have a go with what Wishbone uses.

Example Wishbone-ST slave signals

The following is a typical slave set of signals:

input [18:0] ADR_I,
input CYC_I,
input WE_I,
input [7:0] DAT_I,
output [7:0] DAT_O,
output ACK_O,
output [1:0] IRQ_O,
input [1:0] CLQ_I,
input CLK_I,
input RST_I

This implements an 8-bit interface, with 19-bit address line and read/write capability. Two interrupts are provided.

Example handling

always @(posedge CLK_I)
  case (state_cur)
    if(is_access && access_sram)
      sram_cyc <= 1;
    if(is_access && access_sdram)
      sdram_cyc <= 1;
    if(is_write && access_clut)
      clut_cyc <= 1;
    if(is_access && access_spi)
      spi_cyc <= 1;
      sram_cyc <= 0;
      sdram_cyc <= 0;
      clut_cyc <= 0;
      spi_cyc <= 0;
    sram_cyc <= 0;
    sdram_cyc <= 0;
    clut_cyc <= 0;
    spi_cyc <= 1'b0;

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