SYNTHINGS is a digital synthesizer development platform that I've been building.

Category: SYN1 - Initial test

More complete Wishbone implementation

After writing the previous blog entry, I decided to modify all the modules so they would use the more correct Wishbone CYC_/ACK_ timing model, and also implement the STB_ signals (even though they would be a duplicate of the CYC_ signal).  (More)

My Wishbone implementation (Wishbone-ST)

All of my wishbone modules weren't actually wishbone compatible modules - I'd used some of the basic ideas, and simplified the architecture a bit.  (More)

Getting the SDRAM to work

I had a thought about this while at work yesterday. Everything in the SDRAM code uses positive edge clocks - except for the data reading. With luck, that would be the only thing that needed changing...  (More)


One of my earlier projects had an SPI slave, but this needed to be an SPI master - so I wrote one that had my requirements:  (More)


I hadn't soldered the audio part yet (except for the connectors), so the first job was to solder on the WM8759 and the accompanying resistors, capacitors and inductor.   (More)
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